In the manufacturing of integrated circuits (IC's), the individual devices, such as the transistors fabricated on the silicon substrate, must be connected together with electrical conductors, to perform the desired circuit functions. The process of forming interconnects is generally called metallization.
Metallization consists of many steps that are repeated for each metallization layer. One manner of simplifying the process of metallization is to employ damascene techniques. Instead of, depositing blanket layers and etching away excess metal to provide wiring patterns, damascene processing involves providing templates for wiring and by forming trenches in an insulating layer. Metal overfills the trenches and a polishing step removes the excess metal outside the trenches. Metal is thus left in a desired wiring pattern within the trenches. Where contact holes or vias extending from the floor of the trenches to lower conductive elements are simultaneously filled with metal, the method is known as a dual damascene process.
In damascene structures, the metallization layer is commonly realized by applying copper in order to reduce RC delay. One drawback of using copper interconnects is the rapid diffusion of copper through various dielectric materials that alters the dielectric properties of the device. Therefore, to prevent the diffusion of the copper, one or more liners are formed to provide a diffusion barrier for copper within the trenches and vias prior to metal fill. Low electrical resistivity is desired for the barrier layer in order to reduce the resistance of current flow in Cu interconnects.
Typically, copper is deposited by electrochemical deposition (ECD), which entails a prior conformal and conductive seed layer with low resistivity to cover the area to be coated with copper. A thin Cu film is usually deposited by physical vapor deposition (PVD) as a seed layer prior to ECD processing of copper. Also, a good wetting property of Cu on the barrier layer avoids Cu agglomeration and discontinuity of the seed layer on the barrier, which may affect the subsequent ECD process.
In the subsequent step, the overfilled liner and Cu are removed by chemical mechanical polishing (CMP). It is desirable that the adhesion of Cu to the liner and the adhesion of the Cu/liner film stack to the underlying and surrounding regions is good enough to prevent peeling of the layers and to ensure that the film stack can endure the stress caused by CMP. However, it is particularly difficult to provide a copper layer with good adhesion to the underlying diffusion barrier layer. One approach is to add an adhesion layer between the barrier and Cu seed layers. Good electrical contact between the different layers is also desirable for adequate functioning of the device.
Materials that are suitable to prevent the diffusion of copper include: refractory metals such as Ta, Ti, W, Mo, Co, Cr, Pd, and Nb; metal alloys such as Ta/Ir and Mo/Ni; metal nitride and carbide and boride such as TaNx, TiN, W2N, HfN, TaC, TiC, WCx and TiB2; ternary compounds such as TiN:Six, TaNx:Siy, MoN:Six, and WNxCy and TaCN; and a nanolaminate or a sandwich of materials, such as Ta/Ti, Ta/TaNx, TiN/Ti, TiN/Al, WN/WC, and WN/TiN etc. A diffusion barrier layer is often first deposited over the dielectrics of vias to ensure good electrical contact and good adhesion of the subsequently deposited layers to the underlying regions.
To improve the adhesion of copper to the diffusion barrier layer, an intermediate layer with good adhesion and barrier properties may be deposited prior to any Cu metallization. The adhesion layer may include, for example, metals, metal nitrides and/or alloys. A known adhesion layer is a layer that includes cobalt, cobalt-based alloys, ruthenium, or ruthenium-based alloys, platinum, or platinum based alloys.
The state-of-the-art copper seed layer material is a copper layer deposited by physical vapor deposition (PVD). The following alloys are also known as seed layers: copper-magnesium alloy, copper-tin alloy, copper-aluminum alloy and their nitrogen graded forms. Nitrogen in the copper alloy provides enhanced adhesion of the seed layer to a nitrogen containing barrier layer.
The metallization process may consist of depositing a barrier-adhesion-layer, depositing a copper seed layer, depositing a copper layer by ECD or by chemical vapor deposition (CVD), and planarization by CMP. A feature that enables the fabrication of integrated circuits and ensures high yield and productivity is a good adhesion and wetting of the copper layer to the barrier layer such that it can promote ECD copper deposition and survive the CMP process and other subsequent process steps, including thermal processing at temperature of 400° C. The properties of the copper-barrier interface are also important, since the interface strongly affects the electromagnetic properties of the metallization layer.
The above-described liners occupy a considerable volume of the trenches and that reduces the room available for the more conductive metal filler. Therefore, the conductivity is reduced in relation to the same trenches filled with metal only. Employing metal nitride liners tends to induce electromigration during circuit operation, possibly leading to voids and complete separation of metal lines and further resulting in reduced conductivity of the metal lines and device breakdown.